1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device made up of a Bi-CMOS (Complementary Metal Oxide Semiconductor) integrated circuit composed of a bipolar element and a MOS (Metal Oxide Semiconductor) element in a mixed manner.
2. Description of the Related Art
Generally, the Bi-CMOS requires to fabricate bipolar elements, which are vertically arranged elements, and CMOS elements, which are horizontally arranged element, on a same substrate. This, however, makes the fabrication process complicated and therefore increases the number of fabrication steps.
To overcome this problem, a method was proposed in which, for example, the LDD (Lightly Doped Drain) of a MOS element and the base of a bipolar element are formed at the same time in addition to the well and isolation region-common to these elements such that the advantages of both the elements are preserved, thereby forming the bipolar elements in as small number of fabrication steps as possible by matching the fabrication process to the standard CMOS element forming process.
One example of this will be described with reference to the technology disclosed in Japanese Non-examined Patent Publication No. Hei 6-52778.
The following describes the related-art method of manufacturing a semiconductor device made up of a Bi-CMOS integrated circuit with reference to FIGS. 13 through 19.
Now, referring to FIG. 13, a p-type silicon substrate 101 is formed with an n.sup.+ buried layer 102 and a p.sup.+ buried layer 103, on which an n-type epitaxial layer 104 is formed. Next, a p-type well 105 is formed in an n-channel MOS area and an isolation area. Then, by selective oxidization, a p-type channel stopper 107 and a field oxide film 108 are formed.
Referring to FIG. 14, an element forming area is exposed, on which an oxide film 109 as a gate insulation film is grown by thermal oxidization. Then, a polycrystalline silicon layer 110 is grown all over the oxide film 109 by CVD (Chemical Vapor Deposition), all over which a WSi (Tungsten Silicide) layer 111 is grown by sputtering. Next, patterning is performed and an gate electrode 112 of the MOS element is formed.
Referring to FIG. 15, with a photo resist 106 used as a mask, an impurity such as phosphorus is ion-implanted into a collector leading area of the bipolar element.
Referring to FIG. 16, the ion-implanted impurity is diffused by the thermal treatment in nitrogen atmosphere to form an n.sup.+ diffusion layer 113.
Referring to FIG. 17, with a photo resist used as a mask, an n.sup.- diffusion layer 114 that provides the LDD of an n-channel MOS element and an p.sup.- diffusion layer 115 that provides the LDD of a p-channel MOS element are formed in a self aligning manner. At this moment, a p.sup.- diffusion layer 116 as an intrinsic base of the bipolar element is also formed. Next, an oxide film is grown on all over the surface, then an sidewall oxide film 117 is formed on the side of the gate electrode 112 by reactive ion etching. Then, with a photo resist used as a mask, an n.sup.+ diffusion layer 118 that provides the source and drain of the n-channel MOS element and a p.sup.+ diffusion layer 119 that provides the source and drain of the p-channel MOS element are formed by ion-implantation in a self aligning manner. At this moment, a p.sup.+ diffusion layer 120 as a external base of the bipolar element is also formed.
Referring to FIG. 18, after growing an oxide film 121 on all over the surface by CVD, selective etching is performed to form a window 122 over the intrinsic p.sup.- diffusion base layer 116. Next, a polycrystalline silicon layer is formed on the all over surface by CVD, then an impurity such as arsenic is ion-implanted into the polycrystalline, and thermal treatment is performed.
At this moment, due to diffusion of the impurity from the polycrystalline silicon layer, an n.sup.+ diffusion layer 123 that provides a shallow emitter is formed on the p.sup.- diffusion layer 116. Then, patterning is performed to form an emitter electrode 124.
Referring to FIG. 19, after growing an interlayer insulation film 125 on the main surface, selective etching is performed on the interlayer insulation film 125 to form a contact window 126. Finally, an aluminum layer is formed on the main surface by sputtering and then patterning is performed to form an aluminum electrode 127, completing the Bi-CMOS integrated circuit.
The above-mentioned semiconductor device manufacturing method simplifies the manufacturing process by forming the bipolar element and the MOS element on the same semiconductor substrate as the small number of manufacturing steps as possible.
Conventionally, after forming of the gate insulation film and the gate electrode, phosphorus is implanted into the collector leading area and impurity drive-in step by heat treatment is performed. This is done to prevent as far as possible the ion implantation through the insulation film 109 from causing crystalline defect on the substrate surface and the implanted phosphorus from being diffused out into the gas atmosphere.
However, in the conventional manufacturing method, implanting high-density phosphorus and performing impurity diffusion at high temperatures to further lower the resistance of the collector leading area of the bipolar element hinder the increase in the operation speed and integration of the MOS element.
To be more specific, when high-density phosphorus is implanted into the collector leading area, the oxide film 109 needs to be comparatively thick to prevent crystalline defect from occurring on the substrate surface. However, in the conventional technology, this oxide film and the oxide film that provides the gate insulation film of the MOS element are formed in a same step, thereby making the gate insulation film as thick as the oxide film 109. Consequently, only a dose as small as about 5.times.10.sup.15 atoms/cm.sup.2 can be ion-implanted into the area that provides the collector leading area. This prevents the collector leading area of relatively low resistance from being realized.